1. Field of the Invention
Embodiments of the invention generally relate to methods for depositing materials on a substrate, and more specifically to methods for filling apertures within a contact formed on a substrate.
2. Description of the Related Art
Multilevel, 45 nm node metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology possess features with small CD's and high aspect ratios including contacts, vias, lines and other apertures. Reliable formation of these features is very important for the success of VLSI and the continued effort to increase quality and circuit density on individual substrates. Therefore, there is a great amount of ongoing effort being directed to the formation of void-free features with low contact resistance for the 45 nm node and nodes below.
Tungsten is a choice metal for filling VLSI features, such as sub-micron contact on a substrate. Conventional “contacts” are formed by depositing a conductive interconnect material, such as tungsten into an aperture (e.g., via) on the surface of insulating material disposed between two spaced-apart conductive layers. The aspect ratio of such an opening may inhibit deposition of a conformal conductive interconnect material to fill an aperture. Although tungsten is a popular interconnect material, vapor deposition processes for depositing tungsten commonly suffer from void or a seam type defect creation within the contact plug, as illustrated in FIG. 1C. Also, tungsten is has a relatively high resistivity, which will result in a high circuit resistance formed using the tungsten containing contact.
FIG. 1A depicts a schematic cross-sectional view of an integrated circuit device on substrate 100 containing a via or aperture 105 formed in dielectric layer 104 to expose contact layer 102. During a vapor deposition process that may include chemical vapor deposition (CVD) or atomic layer deposition (ALD), a tungsten layer 106 is deposited on dielectric layer 104 and within aperture 105 including on contact layer 102 and the sidewalls of dielectric layer 104 to form plug 103, as illustrated in FIG. 1B. Near the opening 107 of plug 103, tungsten layer 106 may pinch off, depicted in FIG. 1C, so that plug 103 maintains a seam or a void 108 therein. During a subsequent chemical mechanical polishing (CMP) process that removes a portion of tungsten layer 106 and dielectric layer 104 from the surface of substrate 100, void 108 may be breached or exposed to form gap 110 within plug 103, as illustrated in FIG. 1D. FIG. 1E depicts conductive layer 112 (e.g., copper) deposited on substrate 100 forming void 114 by enclosing gap 110. Substrate 100 may contain additional layers of material depending on the overall architecture of the electronic device. For example, dielectric layer 104 may be covered by a barrier layer (not shown) thereon prior to the deposition of conductive layer 112 and/or conductive layer 112 may also contain a barrier layer (not shown) thereon prior to the deposition of layer 120.
Defects, such as a seam or a void 114, may cause a series of problems during the fabrication of electronic devices depicted herein. The resistance to current flow through the plug 103 is impaired due to the lack of tungsten material in the void 114. However, a more serious obstacle during fabrication is the displacement of voids from one layer to the next. For example, subsequent fabrication processes of substrate 100 may include the deposition of layer 120 (e.g., dielectric layer) on conductive layer 112. During subsequent thermal processing, such as an annealing process, the material 116 from conductive layer 112 may diffuse into void 114 and form a void 118 within conductive layer 112. As illustrated in FIG. 1F, material 116 may not diffuse completely to the bottom of void 114. The defect formed in the conductive layer 112, such as void 118, will increase the resistance of the circuit containing the defect and thus affect device performance. Ultimately, the defects in the conductive layer 112 can affect the device yield of the fabricated substrate. Therefore, there is a need for a method of reliably forming a plug 103 that does not have a seam or void type defect.
Also, one limitation of device performance, or device speed, is related to the resistance of the circuit formed in the semiconductor device. If the geometry of the device(s) remain the same (e.g., trace length, contact feature aspect ratio) the main factor that effects the resistance of a formed circuit is the resistivity of the materials used to form the device. The lower the resistivity, the better one material will perform versus another material. For example, the resistivity of pure tungsten is about 3.3 times higher than the resistivity of pure copper and thus a copper containing device would be faster than a comparable circuit made using tungsten. This among other reasons is often why copper interconnects are formed on integration levels M1 and above. In general, the term metal layer 1, or M1 layer, is generally intended to describe an interconnect layer (e.g., conductive layer 112) formed over the contact level layer, such as a tungsten plug (e.g., plug 103) that is formed during the contact layer formation process. Tungsten is commonly used at the contact level features due to it ability to fill features using CVD processes and it will not rapidly diffuse into silicon and adjacent oxide layers.
Reliably producing nanometer-sized features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of the contact level features (e.g., contacts, vias and other interconnects). Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
Copper has become the metals of choice for nanometer-sized interconnect technology used in the metal layers M1 and above because copper has a lower electrical resistivity than most commonly used metals (e.g., aluminum) and a higher current carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state. Unfortunately, the use of copper at the contact level of a device has a number of drawbacks which include that it rapidly diffuses through silicon and dielectric materials, it has a relatively low melting point which can limit the maximum allowable silicidation formation temperature.
Therefore, there exists a need for an improved contact level device that is void free, that has a low electrical resistance, that has good electromigration performance, that is reliable, and that can be reliably formed.